一种片上可配置安全网络适配器的设计与实现

The design and implementation of a configurable security network adapter on chip

为了满足当前高速网络传输处理中安全性与实时性的要求,以AES-128/192/256算法为基础,设计了一种采用流水可重构技术的AES加/解密IP核,并通过SOPC技术将该IP核、Nios II处理器、网络控制器等功能模块与外围设备进行集成,实现了一个可根据具体应用资源多少与安全系数要求而灵活配置的片上网络适配器.本设计采用硬件描述语言VHDL设计,利用QuartusⅡ8.0进行了综合与布线,最后在DE2实验平台上进行下载测试验证.整个设计硬件结构简单、安全性高、运行速度快、灵活性强,可被广泛应用于网络信息安全领域.

To meet the requirements for real- time and security of high -speed network transmission in the current,we designed a kind of AES encryption/deeryption IP core based on AES -128/192/256 algorithm and using pipeline reeonfigurable structure in this paper. Meanwhile, this IP core, the Nios Ⅱ processor, the network controller, including other function modules and the corresponding gy, implementing a network adapter on chip can according to spec configuration flexible. The design uses hardware description peripherals are integrated by SOPC technolo- ific application resources and safety demand to language VHDL, and layout and wire on Quartus Ⅱ 8.0. Finally the system is downloaded to DE2 for testing. The design rity, high - speed, flexibility, which can be widely used in the field of network hardware structure information security simple, secu-