基于SIMD技术的可重构去块滤波器结构

Architecture of Reconfigutable Deblocking Filter Based on SIMD Technology

由于去块滤波运算数据量庞大的特点以及视频解码实时性的要求,近年来,去块滤波运算的硬件加速器已逐渐成为研究的热点。从兼顾系统的灵活性与性能的角度出发,设计了一种可重构去块滤波器。与传统的支持单一标准的去块滤波硬件加速器相比,该滤波器具有以下优点:实现了一种滤波算法可配置的滤波器结构,从而可以支持多个视频编码标准;采用了基于SIMD单指令多数据流技术,实现滤波数据全并行运算,使硬件高度规整,易于芯片布局布线;设计了1个4级可配置的流水线,重构为不同视频标准的去块滤波器,复用硬件资源,提高了硬件利用率和系统数据吞吐量。用这种架构实现了1个同时支持H.264、AVS、VP8、RealVideo 4种标准的多标准去块滤波加速器,时钟频率为200 MHz,能够用于多标准高清视频的实时滤波处理。

Owing to the data-intensive characteristics of the deblocking filter and the requirement of real-time video decoding,the hardware deblocking filtering accelerator has been recently receiving an increasing attention.Compared with the traditional hardware accelerators which support single standard for deblocking filtering,the proposed reconfigurable deblocking filter in this paper has the following advantages： Implement a deblocking architecture whose filtering algorithm can be reconfigured to support multiple video encoding standards;Adopt SIMD technology to attain the parallel computing of all filtering data,and the chip layout is easily made due to highly regular hardware structures;Design a 4-stage assignable pipeline and reconfigure the deblocking filter for different video standards so as to enhance hardware utilization and system throughput.A multi-standard accelerator deblocking filter supporting H.264,AVS,VP8,and RealVideo standards is implemented with the clock frequency 200 MHz,which can be used for real-time multi-standard HD video deblocking filtering.