VHDL设计中双时钟的实现

Realization of Double Clock in VHDL Design

介绍硬件描述语言的特点和VHDL描述时序逻辑电路时的限定条件,讨论了VHDL描述双时钟时序逻辑电路所遭遇的困难,并给出了两种解决方案.

This paper describes characteristics of VHDL and describes the limitations with VHDL describing liming logic circuit.The difficulties of VHDL describing double-clock timing logic circuit are discussed,and the two solutions are given.