基于虚拟可重构平台的时序电路演化设计

Design of Sequential Circuit Evolution Based on Virtual Reconfigurable Platform

目前,电路进化设计是演化硬件研究的主要方向之一。而时序电路由于存在反馈环不便于进行电路描述和软件仿真。文中对时序电路的演化设计方法进行了改进,提出了专门针对时序电路演化的虚拟可重构平台,建立起电路编码与HDL代码的映射关系。应用TEXTIO和MATLAB来辅助仿真测试过程,使测试向量数量巨大、难以处理的问题得到很好地解决。最后调用ModelSim完成了FSM的演化实验。实验结果验证了基于此平台演化时序电路的可行性和有效性。

At present,design of circuit evolution is one of the main research directions in evolvable hardware.And the sequential logic circuit evolution has always been the key problem of digital circuits evolution research.In this paper,the design method of sequential logic circuit evolution was improved,and the virtual reconfigurable platform was put forward specifically for the evolution of sequential circuit.On the basis of the platform,the one-to-one mapping relationship was set up between circuit coding and HDL code.Apply TEXTIO and MATLAB simulation to assist the test process,which solve the problems of test vector enormous quantity and handle hard.At last,transfer for ModelSim software to complete one FSM evolution experiment.Experimental results show that the model is suitable for the small-scale of the sequential logic circuit evolution.