期刊文献+
任意字段
题名或关键词
题名
关键词
文摘
作者
第一作者
机构
刊名
分类号
参考文献
作者简介
基金资助
栏目信息

CMOS工艺多功能数字芯片的输出缓冲电路设计

Design of multi-functional digital chip's out buffer circuit in CMOS process
下载PDF
导出
摘要 为了提高数字集成电路芯片的驱动能力,采用优化比例因子的等比缓冲器链方法,通过Hspice软件仿真和版图设计测试,提出了一种基于CSMC 2P2M 0.6μm CMOS工艺的输出缓冲电路设计方案。本文完成了系统的电原理图设计和版图设计,整体电路采用Hspice和CSMC 2P2M的0.6μm CMOS工艺的工艺库(06mixddct02v24)仿真,基于CSMC 2P2M 0.6μm CMOS工艺完成版图设计,并在一款多功能数字芯片上使用,版图面积为1 mm×1 mm,并参与MPW(多项目晶圆)计划流片,流片测试结果表明,在输出负载很大时,本设计能提供足够的驱动电流,同时延迟时间短、并占用版图面积小。 In order to improve the driving ability of the digital integrated circuit chip ,by optimizing the scale factor ratio buffer chain method,the design of output buffer circuit based on CSMC 2P2M 0.6 μm CMOS process is designed in this paper by simulation of Hspice Software and layout design testing, The paper complete system of electrical schematic design and layout design.The circuit is simulated using Hspice and the process of the CSMC 2P2M 0.6μm CMOS （06 mixddct02v24）, the layout is based on CSMC 2P2M 0.6 μm CMOS and is used in a Multi-functional Digital Chip, The chip area is 1 mmxl mm. The design has been successfully implemented by participating in the plan of the Multi Project Wafer. Measurements indicate that t the design can provide sufficient drive current, and short delay time, and small layout when the output load is very large.
作者 周子昂 姚遥 徐坤 张利红
机构地区 周口师范学院物理与电子工程系
出处 《电子设计工程》 2012年第5期106-109,共4页 Electronic Design Engineering
基金 周口师范学院青年科研基金(zknuqn201043A)
关键词 CMOS工艺 输出缓冲电路 版图设计 MPW计划 在片测试 CMOS process output buffer circuit layout design MPW on chip test
分类号 TN402 [电子电信—微电子学与固体电子学]
  • 相关文献

参考文献10

  • 1易敬军,沈绪榜.双等比CMOS缓冲器的设计[J].微电子学与计算机,2003,20(1):62-66. 被引量：2
  • 2Linholm L W.An optimized output stage for MOS integratedcircuits[J].1EEE Solid-State Circuits Society,1975,l0(2):106-109.
  • 3Jaeger R C.Omments on an optimized output stage for MOSintegrated circuits[J].1EEE J Solid-State Circuits,1975,10(3):185.
  • 4Li N C,Haviland G L,Tuszynski A A.CMOS tapered bufer[J].IEEE Solid-State Circuits,1990,25(4):1005-1008.
  • 5Prunty C,Ga1 L.Optimum tapered bufer[J].IEEE Solid-StateCircuits,1992,27(1):118-119.
  • 6Hedenstierna N,Jeppson K O.Comments on the optimumCMOS tapered bufer problem[J].IEEE Solid-State Circuits,1994,29(2):155-159.
  • 7Lee C M,Soukup H.An algorithm for CMOS timing andarea optimization[J].IEEE Solid-State Circuits,1984,SC-19(5):781-787.
  • 8Harry V.Deep-submicron CMOS ICs,from basics to ASICs.Second Edition[M].Boston:Kluwer Academic Publishers,2000.
  • 9Glasser L A,Dobberpuhl D W.The design and analysis ofVLSI circuits[M].Reading:Addison-Wesley Publishing Com-pany,1985.
  • 10Annaratone M.Digital CMOS circuit design[M].Boston:KluwerAcademic Publishers,1986.

二级参考文献13

  • 1[1]H C Lin and L W Linholm. An Optimized Output Stage for MOS Integrated Circuits. IEEE J Solid- State Circuits,Apr, 1975,SC- 10(2):106 ～ 109.
  • 2[2]R C Jaeger. Omments on An Optimized Output Stage for MOS Integrated Circuits. IEEE J Solid- State Circuits,June, 1975,10(3):185
  • 3[3]N C Li, G L Haviland, and A A Tuszynski. CMOS tapered buffer. IEEE J. Solid -State Circuits, Aug, 1990,25(4): 1005 ～ 1008.
  • 4[4]C Prunty and L Gal. Optimum tapered buffer. IEEE J Solid - State Circuits, Jan, 1992,27(1):118 ～ 119.
  • 5[5]N Hedenstierna and K O Jeppson. Comments on the optimum CMOS tapered buffer problem, IEEE J. Solid- State Circuits, Feb, 1994,29(2) :155 ～ 159.
  • 6[6]S R Vemuru and E D Smith. Variable taper CMOS buffer design. in Proc 9th Biennial Univ Govt Ind Microelectron.Symp.,1991, 179 ～ 184.
  • 7[7]S R Vemuru and A R Thorbjornsen. Variable -taper CMOS buffer. IEEE J Solid - State Circuits, Sept, 1991,26(9):1265 ～ 1269.
  • 8[8]S R Vemuru and E D Smith. Split - capacitive load variable taper buffer design. in Proc. IEEE Midwest Symp. Circuits Syst., May, 1991, 815 ～818.
  • 9[9]H J M Veendrick. Short - circuit dissipation of static CMOS circuitry and its impact on the design of buffer circuits.IEEE J. Solid-State Circuits, Aug, 1984, SC- 19(4):468 ～ 473.
  • 10[10]J -S Choi and K Lee. Design of CMOS Tapered Buffer for minimum power-delay product. IEEE J. Solid-State Circuits, Sept, 1994,29(9) :1142 ～ 1145.

共引文献1

电子设计工程
2012年 第5期

相关作者

内容加载中请稍等...

相关机构

内容加载中请稍等...

相关主题

内容加载中请稍等...

浏览历史

内容加载中请稍等...
;
使用帮助 返回顶部