一款百万门级SOC芯片的可测性设计

DFT Solution for a Multimillion Gate Design

本文介绍了一款基于65nm工艺的数字处理芯片的可测性设计,采用了边界扫描测试,存储器内建自测试和内部扫描测试技术。这些测试技术的使用为该芯片提供了方便可靠的测试方案,实验结果表明该设计的测试覆盖率符合工程应用要求。

Abstract：This paper present at DFT rcsohltion scheme for a multimillion gate design,based on 65 nm CMOS technology,including boundary scan test, memory built-in self-test and internal scan test. These techniques offer convenient and reliable test scheme for the chip. The results show acceptable test coverage, which meet the requirement of engineering applications.