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抗辐射数字电路加固技术研究 被引量:5

Study of the Radiation-hard Ability of Digital Circuits
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摘要 文章对电路抗辐射的机理进行了研究,提出了几种提高数字电路抗辐射能力的方法:通过工艺控制减小辐射后的背栅阈值电压漂移,通过版图增加体接触、采用环型栅等结构提高单元的抗辐射能力,通过对电路关键节点的加固提高整体电路的抗辐射能力。为了验证加固方法的可靠性,设计了一款电路进行抗总剂量、抗瞬态剂量率、抗中子辐射、抗单粒子辐射等多种试验。通过辐照试验结果可以看到,采用抗辐照方法设计的电路具有较强的抗辐照能力,为今后抗辐照电路的研制和开发奠定了坚实的基础。 In this paper, we studied the mechanism of radiation and offered several optimization methods to improve the radiation-hard ability of digital circuits. According to the research, we decrease threshold voltage excursion by process control, improve the radiation-hard ability by adding body-contact and using roundgate, improve the radiation-hard ability of the key-point. This paper design a digital circuit to validate the radiation-hard method by total dose radiation experiment, trans-radiation experiment, neutron experiment and SEU experiment. According to the experiment results, the radiation-hard ability of the circuit is improved.
出处 《电子与封装》 2012年第2期37-39,48,共4页 Electronics & Packaging
关键词 抗辐射 SOI 总剂量 radiation-hard SOI total dose radiation
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参考文献2

  • 1P.francis,C.Michel,D.Flandre,J.P.Colinge. Radiation-Hard Design for SOI MOS inverters[J]. IEEE Transactions on nuclear science. 1994.41(2).
  • 2陈桂梅,许仲德,苏秀娣.IC抗辐射加固的方法[J].微处理机,1998,19(4):18-19. 被引量:4

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  • 1A. Stabile, V. Liberali, and C. Calligaro. Design of a rad- hard library of digital cells for space applications[M]. in Proc. Int. Conf. on Electronics, Circuits and Systems (ICECS), Malta, Sep. 2008. 149-152.
  • 2D. G. Mavis and D. R. Alexander. Employing radiation hardness by design techniques with commercial integrated circuit processes[C], in Proc. Digital Avionics Systems Conf., 1997.2.1 - 15-2.1-22.
  • 3A.E Singh et al., N.S. Panwar. On Silicon Timing Validation of Digital Logic Gates - A Study of Two Generic Methods[C]. 25th International Conference on Microelectronics, 2006. 424-427.
  • 4F. Wang and V. D. Agrawal. Single Event Upset: An Embedded Tutorial[C]. The 21st International Conference on VLSI Design, Hyderabad, India, 2008. 429-434.
  • 5S. Mitra, M. Zhang, N. Seifert, B. Gill, S. Waqas, and K. S. Kim. Combinational logic soft error correction[C]. International Test Conference, November 2006.
  • 6M. Nicolaidis. Design for soft error mitigation[J]. IEEE Trans. Device Mater. Sep. 2005, 5(3) : 405-418.
  • 7KBORSBID O,CORP S.Selecting charge pump DC/DC converters[J].EDN China,2000,7(8):115-124.
  • 8BAZE M P,BUCHNER S P.Attenuation of single event induced pulses in CMOS combinational logic[J].IEEE Transactions on Nuclear Science,1997,44(6):2217-2223.
  • 9HAZUCHA P,SVENSSON C.Impact of CMOS technology scaling on the atmospheric neutron soft error rate[J].IEEE Transaction on Nuclear Science,2000,47(6):2586-2594.
  • 10CALIM T,NICOLAIDIS M,VELAZCO R.Upset har dened memory design for submicron CMOS technology[J].IEEE Transaction on Nuclear Science,1996,43(6):2874-2878.

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