SM3算法的FPGA设计与实现

Design and implementation of SM3 algorithm on FPGA

在分析SM3算法的基础上详细介绍了目前Hash函数的4种硬件实现策略,同时给出了迭代方式和基于充分利用时钟周期的循环展开方式下的FPGA实现。该循环展开方式有效地减少了一半的工作时钟数和11%的运算时间,吞吐量提高了11%,且占用的硬件资源较少。

This paper introduces four ways of the Hash function hardware implemention based on the SM3 algorithm and the iterative way. And FPGA realization is given based on the sufficient use of the clock cycle circle-unroll way. This circle-unroll way availably reduces the number of work clock cycle into half and 11% operation times consumption, improves 11% throughput and occupies little hardware resource.