基于FPGA的小数频率合成器的设计

The Design and Simulation Approach for Fractional-N Frequency-synthesizers

小数分频是实现高分辨率低噪声频率合成器的主要技术手段。在分析了小数频率合成以及杂散抑制技术的基础上,采用高阶Σ-Δ调制技术可以将量化噪声功率的绝大部分移到信号频带之外,从而可通过滤波有效抑制噪声。仿真结果表明,该高阶数字Σ-Δ调制可以很好地抑制小数分频频率合成器中的杂散问题,具有很高的实用性。

The fractional-N frequency synthesis is one of the most important techniques to realizing the frequency synthesizer with fine frequency resolution and low phase noise.In this paper,the higher-order sigma-delta modulator is proposed.It can suppress noise by the loop filter of the phase-locked-loop.The simulation show that the noise is suppressed and it is highly practicable.