基于MCU的锁相环锁定时间测量系统设计

Design for measurement system of PLL lock time based on MCU

为测量锁相环锁定时间,通过比较各锁相环芯片的接口特点,设计通用的测量系统。该系统包括上位机、下位机软件以及基于AT89C51的控制电路,上位机和下位机使用串口通信。通用性和实时性是系统最大特点,在软件和硬件的设计上保证系统能兼容大多数常用锁相环芯片;并能根据用户输入的控制参数实时控制锁相环且测量其锁定时间。通过实际应用证明,该系统能准确测量锁定时间,有效减少锁相环设计与调试过程中的工作量与复杂度。

A measure the lock universal measurement system was design by comparing the interface characteristics of each PLL chip to time of circuit based on AT89C5 PLL. T 1. The his system includes the softwares for both upper computers and lower computers, and control port communication is adopted for upper computers and lower computers. The generality and real-time performance are the primary features of this system to guarantee the compatibility of most common PLL chips in the design of softwares and hardwares. This system can control PLL and measure lock time of it timely according to the control parameter which is input by users. The actual application demonstrates that this system can not only measure the lock time of PLL precisely, but also reduce the work load and complexity during the design and debugging of PLL.