基于改进DA算法和流水线技术的FIR数字滤波器设计

Design of FIR Digital Filter Based on Improved DA and Pipeline

提出了一种改进的分布式算法和一种具有流水线结构的加法树乘法器,设计了一种在FPGA上实现的FIR数字滤波器。介绍了改进的DA算法,对采用FPGA实现直接型结构移位相加乘法器FIR滤波器和改进DA算法的高速FIR滤波器的性能进行了比较。用VHDL在Quartus II平台上进行了仿真,给出了实现高效滤波功能的设计结果及不同算法的资源占用比较。

A new structure of finite impulse response （FIR） filter based on Frt, A is presented. High speed is achieved by using improved distributed arithmetic （DA） and pipeline multiplier with look-up table by replacing the conventional structure. The principle of improved distributed arithm is described and performances of FIR filters using MAC architecture and new structure implemented in FPGA are compared. Finally, the design is compiled and synthesized with VHDL in quartus II and the simulation waveform is provided.