一种专用可重配置的FPGA嵌入式存储器模块的设计和实现

The Design and Implement of a Special Reconfigurable FPGA Embedded BRAM

本文设计了一种满足FPGA芯片专用定制需求的嵌入式可重配置存储器模块.一共8块,每块容量为18Kbits的同步双口BRAM,可以配置成16K×1bit、8K×2bits、4K×4bits、2K×9bits、1K×18bits、512×36bits六种不同的位宽工作模式;write-first、no-change两种不同的写入模式.多个BRAM还可以通过FPGA中互连电路的级联来实现深度或宽度的扩展.本文重点介绍实现可重配置功能的电路及BRAM嵌入至FPGA中的互连电路.采用SMIC 0.13μm 8层金属CMOS工艺,产生FDP-II芯片的完整版图并成功流片,芯片面积约为4.5mm×4.4mm.运用基于March C+算法的MBIST测试方法,软硬件协同测试,结果表明FDP-II中的BRAM无任何故障,可重配置功能正确,证实了该存储器模块的设计思想.

A customized reconfigurable embedded Block RAM module for FPGA chip is proposed. The number of BRAM is eight and each module is a synchronous dual-port memory cell with the capacity of 18Kbits. The BRAM can be configured as six bit width modes including 16K × 1bit,8K × 2bits,4K × 4bits,2K × 9bits, 1K × 18bits,512 × 36bits; two write modes such as write-first, no-change. Several BRAM can be cascaded through interconnect circuit to achieve the expansion in depth or width. This paper focuses on the circuit that can realize the reconfiguration function. SMIC 0.13um 8-layer metal CMOS process is applied to produce the complete layout of FDP-H chip and then tape-out. The chip area is about 4.5mm × 4.4mm and tested by cooperating with its software system which applies March C ＋ algorithm based MBIST test method. The test results show that BRAM in FDP-II has no fault and the function of reconfiguration work correctly, the design theory of such memory are verified.