可重构处理器的AVS高清解码探究

Research of audio video standard(AVS) HD decoding based on a reconfigurable processor

面向新型可重构处理器架构、动态配置、多任务调度和运行管理嵌入式高性能并行计算关键技术,提出了一种新的针对AVS(audio video coding standard)高清视频解码的实现方案.该方案是将AVS解码过程中的各种算法,映射到一个可重构处理器Remus(reconfigurable multimedia system)上,并通过仿真验证,在200MHz的工作频率下,实现了1080p的AVS高清码流实时解码(30f/s).基于可重构处理器的AVS解码实现方案,比目前市场上已存在的基于ASIC的多种高清解码方案具有更好的灵活性,而具体到解码过程中的典型算法,特别是循环计算,比现有的已提出的硬件加速器具有更好的加速性能.

According to key technologies of embedded high-performance parallel computing for a new reconfigurable processor architecture, dynamic configuration, multi-task scheduling, and operational management, a new methodof AVS HD decoding implementation was proposed in this paper. The decoding process was based on a reconfigu- rable system known as Remus （reconfigurable multimedia system）. By mapping the algorithms of AVS to Remus, the system could support 1080p （30 f/s） real-time decoding of the AVS JiZhun profile at 200 MHz; this was prov- en by simulation. The reconfigurable technology based decoding system is much more flexible than the existing sys- tem and is mostly based on the application specific integrated circuit （ASIC）, with an even higher-level performance of acceleration than the existing hardware accelerator, especially in cyclic computing.