FPGA中单精度浮点乘法器的实现

设计了一个基于FPAG的单精度浮点乘法器,利用了Booth-2算法编码运算,并使用了Wallace树结构完成部分积的累加,并且考虑了浮点数特殊值的处理。乘法器在Xilinx ISE 9.1中进行了综合与仿真,在modelsim中验证了乘法器的正确性。

Based on FPGA,a single precision floating-point multiplier is presented,which uses Booth-2 algorithm to encode multiplying,adopts Wallace tree structure to accumulate partial arithmetic products and can process special values.The presented multiplier is synthesized and simulated in Xilinx ISE 9.1 and the effectiveness of the multiplier is tested in modelsim