电流返回路径分解的信号完整性分析方法

A New Method to Simulate Signal Integrity Based on Return Current Paths Decomposed in High Speed Circuits

提出了一种适用于高速互连电路的信号完整性快速仿真方法。根据电流返回路径不同,该方法将有过孔的三维互连结构分解为电源平面对阻抗模型和微带线模型,先单独分析两种模型特性,再级联以求解整个互连结构特性。与全波仿真方法相比,本方法在保证准确度的前提下可将仿真时间从95 min降低至1 min以内。分析了电路板参数、去耦电容和短路孔对信号完整性的影响,结果表明插入损耗由电源平面结构在过孔位置处的自阻抗决定。在工程设计中,可采用减小电源平面对结构厚度、添加去耦电容和选择适当的过孔位置等方法提高信号完整性。

A new method based on return current paths decomposed is proposed for efficient simulation of signal integrity in high speed circuits. The 3D interconnect structure with vias is first decoupled into power- ground plane pair and microstrip line structure, and each part is solved by analytical methods. Finally, the equivalent circuits of each parts are integrated to simulate the system performance. Compared with full wave simulation, the simulation time is reduced from 95 minutes to 1 minute with considerable accuracy, The structure of printed cir- cuit board, decouple capacitors and shorting vias which affect the system performance are analysed and it is found that the insertion loss is determined by the self - impedance of power ground plane at the location of vias. In engineering design, the signal integrity can be improved through such methods as decreasing dielectric layer thickness, adding decoupling capacitors and adjusting the locations of the vias.