摘要
通过分析分组密码算法中矩阵乘法运算的设计原理和特点,结合逻辑电路结构特征,提出一种可重构矩阵乘法硬件架构的设计原理及方法.电路模拟结果显示,按此原理设计的运算电路在保持运算电路高效性的同时,提高了硬件电路的灵活性.
On the basis of analyzing the theories and characterist ics of matrix multiplicative which is used in block ciphers and the characters o f logic circuit,the authors presented a theory and method of designing a dynami c reconfigurable hardware architecture of matrix multiplicative.The analog circ uit on computer proves that the circuit which is designed according to the metho d presented in this paper is effective in keeping the efficiency of circuit and improves the flexibility of the circuit.
出处
《吉林大学学报(理学版)》
CAS
CSCD
北大核心
2012年第2期191-194,共4页
Journal of Jilin University:Science Edition
关键词
分组密码
矩阵乘法
有限域
block cipher
matrix multiplicative
galois field