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一种多路时间序列控制仪的设计与实现 被引量:6

The Design and Realization of Multichannel Time Sequence Control Instrument
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摘要 为满足兵器试验中多台设备在不同时刻启动工作的需求,研制了一种多路时间序列控制仪.控制仪由单片机控制电路、时序电路控制模块、输入输出隔离电路以及通讯电路组成,控制仪在接收到启动触发信号后,单片机与FPGA组成的时序电路控制模块根据预先设定延时值输出延时触发信号,经驱动后触发测试设备工作.延时值通过计算机或仪器面板上拨码盘输入.设计的时序控制仪可实现20路独立延时通道,每路可在0~10s(最小步进单位100ns)范围内可调,输出延时触发信号幅度最大为12V,输出脉冲宽度为5ms,延时误差优于2μs. In order to meet the requirements of different equipments at different time in weapons test experiment,a kind of multichannel time Sequence control instrument has been developed.The controller consists of MCU control circuit,the control module of sequential circuit,input and output isolation circuits and communication circuit.After receiving the starting trigger signal,according to the pre-set delay time,the control module of sequential circuit,comprising MCU and FPGA,exports the delay trigger signal.The measurement instruments starts working after being trigged by the delay trigger signal which is driven by driving circuit.The values of the delay time were input by the computer or BCD-code-wheel on the instrument panel.The designed time sequence control instrument can realize the output of 20 channels delay trigger signal which can export separately,and every channel can delay from 0 μs to 10 s.Time delay error is less than 2 μs.
出处 《西安工业大学学报》 CAS 2012年第2期87-92,共6页 Journal of Xi’an Technological University
基金 国家自然科学基金资助(60972005) 陕西省教育厅项目资助(2010JK583) 西安工业大学"兵器靶场光电测试技术"科研创新团队建设计划资助
关键词 时序控制 FPGA 延时电路 多机通讯 time-sequence control FPGA delay circuit multi-computer communication
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