NMOS管Snapback特性ESD仿真模型研究

Modeling NMOS Snapback for ESD Simulation Using Advanced Compact Models

随着集成电路特征尺寸的不断缩小,ESD的问题始终困扰着芯片设计师们。文章提出了一种宏模型用于ESD的snapback仿真,它包含一个MOS管、一个NPN晶体管和一个衬底电阻,没有外部的电流源。简化的宏模型没有必要使用行为级的语言,如Verilog-A、VHDL-A。这使得仿真速度和收敛性得到提高。同时比较了三种先进的BJT模型:VBIC、Mextram、HICUM。模型参数可以通过模型参数提取软件(BSIMProPlus、ICCAP等)提取。

As technology feature sizes move into the deep submicron regime,conerns regarding ESD by chip designers is increasing.This paper presents a macro model approach for modeling ESD snapback.It includes a MOS transistor,a NPN transistor and a resistor for substrate resistance.No external current source is included.The simplicity of the presented macro model makes behavior languages,such as Verilog-A,VHDL-A,not necessary in model implantation.It has the advantages of high simulation speed and less convergence issues.The paper also distinguishes three advanced BJT compact models（VBIC,Mextram,HICUM）for ESD snapback simulation.The model parameters can be extracted using software,such as BSIMProPlus,ICCAP.