Amodgen:基于约束的CMOS模拟电路器件版图生成器

Amodgen: Constraints Based Device Generator for CMOS Analog Layout

器件版图生成是模拟电路版图设计自动化的关键问题之一．为了使ＭＯＳ器件版图的性能、形状、面积能在生成阶段得到综合优化，从而有助于解决高层次的模拟电路模块间的布局和布线问题，提出了一种新的模拟电路器件版图生成方法，并开发了基于几何约束、寄生约束、匹配约束的模块生成器Ａｍ ｏｄｇｅｎ．Ａｍ ｏｄｇｅｎ 针对不同的器件采用不同的版图结构，如ＭＯＳ晶体管的交指（ｉｎｔｅｒｄｉｇｉｔｉｚｅ）结构，电容的同心阵列结构，电阻垂直排列的交织（ｉｎｔｅｒｌｅａｖｅ）结构等，这些结构可以减小因集成电路制造工艺不均匀带来的器件失配误差．同时，Ａｍ ｏｄｇｅｎ 还应用哑元条来消除边缘相关的横向刻蚀效应对器件精度的影响．基于约束的生成方法和优化版图结构技术的结合，使Ａｍ ｏｄｇｅｎ 可以快速、高效地生成符合电路性能要求的版图．

The layout generation of analog devices is one of the key problems in analog layout automation. To optimize the performance, shape and area of the layout of MOS devices and to make the placement and routing easier at higher level, a new methodology for analog module generation is proposed. Based on geometry constraints, parasitic constraints and matching constraints, a module generator, Amodgen, is developed. Specifically, interdigitize structures, common centroid and interleave structures are used to minimize the mismatch between matched components in the layout. Dummy stripes are used to minimize boundary dependent under cut effects.