FPGA动态高速加载的设计与实现

Design and Implementation of Fast Dynamic Loading to FPGA

针对现场可编程逻辑阵列(FPGA)动态高速加载问题,设计了一种基于可编程逻辑器件(CPLD)和闪存(FLASH)芯片的动态加载方案,介绍了设计方案、系统硬件连接图及典型的应用案例,并对具体的配置流程、详细的时序设计、软件实现流程进行了介绍。该方法相对传统的配置方法具有加载速度快、存储空间大和使用灵活等优点,方便FPGA在线升级和动态加载,在依据应用环境更改FPGA配置的软件无线电平台上,有较好的应用前景。

A fast dynamic loading method to FPGA based on CPLD and FLASH is designed. In this paper, design project, system connection map and typical application are presented, and the loading flow and timing design are introduced in detail. Compared with other loading methods, this means has more memory and flexibility. It＇s convenient for FPGA to update and configure dynamically online. A good application foreground in Software Radio based on FPGA can be achieved by this means.