高精度SC PIPELINED ADC预放大锁存比较器的分析与设计

Analysis and design of preamplifier-latch comparator for high accuracy switched-capacitor pipelined ADC

提出了一种应用于开关电容流水线模数转换器的CMOS预放大锁存比较器。比较器采用了交叉耦合负载、PMOS/NMOS比例优化和电容中和技术。该结构大幅提高了比较器的速度并有效抑制了回馈噪声,减小了失调电压,可以作为Flash ADC应用于高精度开关电容流水线ADC。

To be compatible with switched capacitor pipelined ADC, a CMOS preamplifier-latch comparator is designed and well analyzed for high speed, low kick-back noise and low mismatch offset. The cross-coupled load, capacitor neutralization and the optimizing ratio of PMOS/NMOS are adopted in the comparator. Since the proposed architecture is effective for achieving, the comparator has been used in high accuracy switched-capacitor pipelined ADC as Flash ADC