eDRAM高速读写和紧凑式电荷转移刷新方案

An eDRAM with Logic Technology Using High-Speed R/W and Compact Charge Transfer Refresh Scheme

提出了一种采用逻辑工艺、访存速度优化、降低刷新功耗的动态随机存储器(DRAM),使其在嵌入式系统的设计与制造中易于与高性能逻辑电路融合.采用读写前置放大的高速读写方案,使DRAM读写速度得到了优化;采用紧凑式电荷转移刷新替代传统刷新方案,在降低了刷新功耗的同时,缩短了DRAM的刷新时间开销,提高了DRAM的数据可访问性.仿真结果表明:与传统方案相比,在3ns时钟周期下,存储器写操作时间为3ns,减少了23%;数据访问时间为1.8ns,减少了15%;在刷新模式下,灵敏放大器功耗降低了58%,同时刷新时间降低了43%.

An embedded DRAM with logic technology using high-speed read/write and low power refresh scheme is proposed.The logic technology enables DRAM easier to merge with high performance logic circuits in design and fabrication of embedded systems.Adopting read/write pre-amplifier scheme optimizes the operation speed of the memory.Compact charge transfer refresh is used to replace conventional scheme so as to reduce the refreshing power and time of the memory,thus the data availability of DRAM is improved.With 3ns clock cycle,the simulation results illustrate that the write cycle of memory is 3 ns and is 23% reduced,meanwhile the access time is 1.8 ns and is 15% reduced,compared with the conventional scheme.The refreshing power and time are 58% and 43% reduced respectively,compared with the conventional scheme.