摘要
针对可进化硬件(EHW)系统的需求,设计实现了FDP-2-SOPC芯片,芯片中嵌入了CPU和FPGA两种IP核,可实现硬件电路的重构和进化;以该芯片为系统核心建立了一种新型的软硬件结合的单芯片级EHW系统.为了提高电路重构速度,设计了针对EHW需求的快速局部重配置技术;为提高遗传算法的执行速度,设计了专用的随机数产生器;为了减少软硬件开发相关性并降低系统开发的难度,满足不同适应度评估方案的需求,提出了一种灵活友好的数据交互技术;并开发了合适的遗传算法.在此单芯片级EHW系统上进行了电路自进化实验,实验结果表明,该系统可正确地实现硬件电路的自重构、自进化,在进化速度上优势明显:针对同样的目标电路进化,在进化算法性能相近的前提下,该系统的进化时间相比FPGA+PC系统提高了一个数量级.
To meet the requirement of the evolvable hardware(EHW)system,the FDP-2-SOPC chip was designed and implemented,in which a PowerPC405 IP core and a self-developed FPGA IP core were embedded for reconfiguration and evolution.Based on the system,an on-chip EHW system was built.To accelerate the reconfiguration,a quick partially reconfiguration technique was proposed,and a dedicated random number generator was designed to accelerate the genetic algorithm.To make the software/hardware co-developing easier and meet the requirement for different fitness evaluation strategy,a flexible and user-friendly interface for data exchanging was proposed.A proper genetic algorithm on this system and some EHW experiments were carried out.Results have showed that the proposed on-chip EHW system works correctly in the EHW application and is fast in evolving.When evolving towards the same target circuit and with a similar algorithm performance,the proposed system is an order of magnitude faster than the PC-FPGA joint system.
出处
《复旦学报(自然科学版)》
CAS
CSCD
北大核心
2012年第1期43-49,76,共8页
Journal of Fudan University:Natural Science
基金
国家高技术研究发展计划("863"计划)(2007AA01Z285)资助项目