摘要
基于0.6μm BiCMOS工艺,设计了一个低功耗14位10MS/s流水线A/D转换器.采用了去除前端采样保持电路、共享相邻级间的运放、逐级递减和设计高性能低功耗运算放大器等一系列低功耗技术来降低ADC的功耗.为了减小前端采样保持电路去除后引入的孔径误差,采用一种简单的RC时间常数匹配方法.仿真结果表明,当采样频率为10MHz,输入信号为102.5kHz,电源电压为5V时,ADC的信噪失真比(SNDR)、无杂散谐波范围(SFDR)、有效位数(ENOB)和功耗分别为80.17dB、87.94dB、13.02位和55mW.
A low power 14 bit 10MS/s pipelined analog-to-digital converter(ADC) using 0.6 μm BiCMOS process is presented.Some methods to realize low power pipelined ADC will be proposed.These methods include removing the active S/H,sharing the op-amp between adjacent multi-bit-per-stages,scaling down and designing high performance low power operation amplifier technique.To reduce aperture error without the active S/H,a simple RC time constant matching method is used.Simulation results show that a SNDR of 80.17 dB,a SFDR of 87.94 dB,and an ENOB of 13.02 bits are achieved.The ADC consumes 55 mW at 5 V supply.
出处
《微电子学与计算机》
CSCD
北大核心
2012年第4期49-52,57,共5页
Microelectronics & Computer