期刊文献+

Sigma-Delta小数分频频率综合器系统建模和仿真 被引量:2

System Modeling and Simulation of Sigma-Delta Fractional-N Frequency Synthesizers
下载PDF
导出
摘要 行为级仿真平台的建立,可以对小数频率综合器的设计提供快速全面的时域仿真.重点分析了2/3多模可编程分频器和MASH结构调制器电路,并给出了一种计算环路滤波器参数的新型工程方法.建立了的Simulink仿真模型,可用于检验电路结构的正确性. The establishment of behavioral-level system simulation platform can provide the accurate and overall time-domain simulations for Fractional-N Frequency Synthesizers design.It laid special stress on analyzing the 2/3 multi-modulus programmable divider and MASH Σ modulator.A new approach for calculating the parameters of loop filter was given.A set of Simulink circuit modes was designed.These modes structure an integrity Σ Fractional-N Frequency Synthesizers which can be used to predict and verify the circuit topologies in practice.
出处 《微电子学与计算机》 CSCD 北大核心 2012年第4期80-83,共4页 Microelectronics & Computer
关键词 Σ-Δ 频率综合器 2/3多模可编程分频器 MASH 环路滤波器 Simulink Σ-Δ frequency synthesizers 2/3 multi-modulus programmable divider MASH loop filter Simulink
  • 相关文献

参考文献6

  • 1Behzad Razavi.射频微电子[M].北京:清华大学出版社,2003.
  • 2池保勇余志平.CMOS射频集成电路分析与设计[M].北京:清华大学出版社,2006.
  • 3杨洪文,高海军,郭桂良,朱思奇,易青,阎跃鹏.基于Simulink的∑△小数N频率综合器行为级仿真[J].微电子学与计算机,2008,25(6):67-70. 被引量:1
  • 4Keliu Shu, Edgar Sanchez-Sinencio. CMOS PLL synthesizers: analysis and design[M]. Berlin: Springer, 2005.
  • 5Philip Quinlan, Patrick Crowley. A multimode 0.3200kb/s transceiver for the 433/868/915-MHz bands in 0. 25urn CMOS[J]. IEEE Journal of solid-state circuits, 2004,39(12) .2297-2310.
  • 6Michael H Perrott, Theodore L Tewksbury, Charles G Sodini. A 27mW CMOS {ractional-N synthesizer using digital compensation for 2.5Mb/s GFSK modulation[J]. IEEE Journal of solid-state circuits, 1997,32 (12) : 2048-2060.

二级参考文献7

  • 1乔文浩,邹务金.基于Verilog-A的电荷泵锁相环行为级建模和模拟[J].微电子学与计算机,2003,20(B12):60-62. 被引量:1
  • 2Behzad Razavi.射频微电子[M].北京:清华大学出版社,2003.
  • 3Brigati S,Francesconi F.Modeling of fractional-N division frequency synthesizers with SIMULINK and MAT-LAB[C]//The 8th IEEE International Conference on Electronics,Circuits and Systems.Malta,2001:1081-1084.
  • 4Perrott M H.Fast and accurate behavioral simulation of fractional-N frequency synthesizers and other PLL/DLL circuits[C]//Proceedings of the 39th Design Automation Conference.New Orleans,2002:498-503.
  • 5Kundert K.Predicting the phase noise and jitter of PLLbased frequency synthesizers[EB/OL].[2006-12-10].www.designers-guide.com.
  • 6Mao Xiaojian,Yang Huazhong,Wang Hui.Behavioral modeling and simulation of jitter and phase noise in fractional-N PLL frequency synthesizer[C]//Proceedings of the 2004 IEEE International Behavioral Modding and Simulation Conference.San Jose,2004:25-30.
  • 7Cassia M,Shah P,Bruun E.Analytical modd and behavioral simulation approgch for a∑△ fractional-N synthesizer employing a sample-hold element[J].IEEE Transactions on Circuits and Systems Ⅱ:Analog and Digital Signal Processing(S1057-7130),2003,50(11):850-859.

共引文献1

同被引文献4

引证文献2

二级引证文献1

相关作者

内容加载中请稍等...

相关机构

内容加载中请稍等...

相关主题

内容加载中请稍等...

浏览历史

内容加载中请稍等...
;
使用帮助 返回顶部