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A constant loop bandwidth fractional-N frequency synthesizer for GNSS receivers 被引量:2

A constant loop bandwidth fractional-N frequency synthesizer for GNSS receivers
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摘要 A constant loop bandwidth fractional-TV frequency synthesizer for portable civilian global navigation satellite system(GNSS) receivers implemented in a 130 nm 1P6M CMOS process is introduced.Via discrete working regions,the LC-VCO obtains a wide tuning range with a simple structure and small VCO gain.Spur suppression technology is proposed to minimize the phase offset introduced by PFD and charge pumps.The optimized bandwidth is maintained by an auto loop calibration module to adjust the charge pump current when the PLL output frequency changes or the temperature varies.Measurement results show that this synthesizer attains an in-band phase noise lower than -93 dBc at a 10 kHz offset and a spur less than -70 dBc;the bandwidth varies by±3%for all the GNSS signals.The whole synthesizer consumes 4.5 mA current from a 1 V supply,and its area(without the LO tested buffer) is 0.5 mm^2. A constant loop bandwidth fractionalN frequency synthesizer for portable civilian global navigation satellite system (GNSS) receivers implemented in a 130 nm 1P6M CMOS process is introduced. Via discrete work ing regions, the LCVCO obtains a wide tuning range with a simple structure and small VCO gain. Spur suppression technology is proposed to minimize the phase offset introduced by PFD and charge pumps. The optimized band width is maintained by an auto loop calibration module to adjust the charge pump current when the PLL output frequency changes or the temperature varies. Measurement results show that this synthesizer attains an inband phase noise lower than 93 dBc at a 10 kHz offset and a spur less than 70 dBc; the bandwidth varies by 4 3% for all the GNSS signals. The whole synthesizer consumes 4.5 mA current from a 1 V supply, and its area (without the LO tested buffer) is 0.5 mm2.
出处 《Journal of Semiconductors》 EI CAS CSCD 2012年第4期117-123,共7页 半导体学报(英文版)
关键词 GNSS接收机 频率合成器 环路带宽 恒定 全球导航卫星系统 LCVCO 分数 CMOS工艺 constant loop bandwidth GNSS frequency synthesizer VCO
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参考文献14

  • 1Wang Xiao,Wang Yuji,Wang Weiwei. Analysis and design of a 1.8-2.7 GHz tunable 8-band TDD LTE receiver front-end[J].Journal of Semiconductors,2011,(05):055006.doi:10.1088/1674-4926/32/5/055006.
  • 2Yang Guang,Yao Wang,Yin Jiangwei. A 3.1-4.8 GHz CMOS receiver for MB-OFDM UWB[J].Journal of Semiconductors,2009,(01):015005.doi:10.1088/1674-4926/30/11/116001.
  • 3Gupta M,Song B S. A 1.8-GHz spur-cancelled fractional-N frequency synthesizer with LMS-based DAC gain calibration[J].IEEE Journal of Solid-State Circuits,2006,(12):2842.doi:10.1109/JSSC.2006.884829.
  • 4Kim J,Horowitz M A,Wei G Y. Design of CMOS adaptivebandwidth PLL/DLLs:a general approach[J].IEEE Journal of Solid-State Circuits,2003.860.
  • 5Wu T,Hanumolu P K,Mayaram K. Method for a constant loop bandwidth in LC-VCO PLL frequency synthesizers[J].IEEE Journal of Solid-State Circuits,2009.427.doi:10.1109/JSSC.2008.2010792.
  • 6ICG. Report on Current and Planned Global and regional Navigation Satellite Systems and Satellite based Augmentation Systems 2010[OL].http://www.unoosa.org/pdf/publications/icg_ebook.pdf,.
  • 7Banerjee D. PLL performance,simulation,and design[M].LLC:Dog Ear,2006.
  • 8Xiao Shimao,Ma Chengyan,Ye Tianchun. A novel 2.95-3.65 GHz CMOS LC-VCO using tuning curve compensation[J].Journal of Semiconductors,2009,(10):105001.doi:10.1088/1674-4926/30/10/105001.
  • 9Rhee W. Design of high-performance CMOS charge pumps in phase-locked loops[A].1999.545.
  • 10Razavi B. Design of analog CMOS integrated circuits[M].New York:McGraw-Hill,2001.

同被引文献13

  • 1Musa A, Murakami R, Sato T, et al. A low phase noise quadrature injection locked frequency synthesizer for MM-wave applications[J]. IEEE Journal of Sol- M-State Circuits, 2011, 46(11 ): 2635-2649.
  • 2Hwang M S, Kim J, Jeong D K. Reduction of pump current mismatch in charge-pump PLL[J]. Electron- ics Letters, 2009, 45(3) : 135 - 136.
  • 3Gardner F M. Charge-pump phase-lock loops[J]. IEEE Transactions on Communications, 1980, 28( 11 ) : 1849 - 1858.
  • 4Rhee W. Design of high performance CMOS charge pumps in phase-locked-loops [C ]//Proceedings of the 1999 IEEE International Symposium on Circuits and Systems VLSI. Orlando, FL, USA, 1999, 2: 545- 548.
  • 5Huang Q T, Rogenmoser R. Speed optimization of edge-triggered CMOS circuits for gigahertz single- phase clocks [J]. IEEE Journal of Solid-State Cir- cuits, 1996, 31(3): 456-465.
  • 6Wang C C, Wu J C. Efficiency improvement in charge pump circuits [J]. IEEE Journal of Solid-State Cir- cuits, 1997, 32(6) : 852 -860.
  • 7Johns D, Martin K. Analog integrated circuit design [M]. New York: John Wiley &Sons, 1997:266 - 273.
  • 8薛红,李智群,王志功,李伟,章丽.低杂散锁相环中的电荷泵设计[J].Journal of Semiconductors,2007,28(12):1988-1992. 被引量:11
  • 9周建政,王志功,李莉,王科平.DRM接收机射频前端芯片的频率规划设计[J].高技术通讯,2008,18(5):480-486. 被引量:6
  • 10黄爱波,何伟,周进,田亮,陈磊,赖宗声.低杂散锁相环中电荷泵的设计[J].微电子学,2009,39(6):798-801. 被引量:3

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