BELLEII实验高速数据接收板的设计

The Design of High Speed Link Board in BELLEII

在高能物理实验中,随着加速器和探测器性能的提高,数据获取系统正面临着越来越大的海量数据实时可靠传输的挑战。BELLEII探测器是运行在SuperKEKB高亮度加速器上的新型探测器,其数据获取系统也面临这一难题。基于FPGA的高速数据接收模块(HSLB)作为数据获取系统的数据传输核心,采用RocketIO技术实现高速串行数据传输,满足速率3.125 Gbps的设计要求;与专用接口连接的CPLD作为控制芯片在线配置FPGA固件,提供快速硬件程序加载,高速链路共享,高速数据传输和慢控制命令传输的功能。论文详细描述了高速数据传输模块的硬件设计、在线配置FPGA的实现方案。经过测试,该模块成功实现设计目标,并已经按工程进度进行了小批量生产。

With the improved performance of accelerators and detectors in the high energy physics experiments,data acquisition（DAQ） system is facing more and more challenges of real time and reliable data transmission.BelleII,as a new type detector running on the high luminosity accelerator SuperKEKB,its DAQ system is facing the same pressure.The high speed link board（HSLB） has achieved a serial line rate up to 3.125 Gbps with the RocketIO technology based on Xilinx FPGA.The control chip CPLD connects to local interface,provides the function such as fast online FPGA configuration,high speed link data transmission and slow control.The HSLB hardware design and FPGA online configuration are introduced in the paper.The test results show that the HSLB can fulfill the critical requirements and small scale mass production is in schedule.