基于FPGA和MCU的低成本地震信号数字滤波器设计

A Low Cost Digital Filter Design for Seismic Data Acquisition Based on FPGA and MCU

针对地震数据采集系统提出一种低成本、高灵活性的数字滤波设计方案。不仅对于地震数据采集系统有很大的实用意义,对于其它传感器网络也是可供参考的解决方案。设计的目的是在保持优秀的低通性能的同时实现高度抽取。该滤波器系统由四级CIC滤波和两级FIR滤波构成,分别在FP-GA和MCU内部实现。滤波器有着良好的低通性能,在430 Hz～500 Hz范围内幅度响应下降了137 dB。采用实际信号测试,信噪比好于110 dB,能够很好地满足地震数据采集的需求。

A low cost and flexible digital filter solution for seismic data acquisition is put forward to improve performance of seismic data acquisition equipment.The purpose is to keep low frequency signal and realize high rate decimation at the same time.The digital filter system consists of four CIC filters which are realized in FPGA and two FIR filters which are realized in MCU.The CIC filters primary purpose is to attenuate out-of-band noise components from the modulator.The FIR filters compensates for SINC filters droop and creates a low-pass corner to block aliased components of the input signal.The digital filter has a good low-pass bandwidth performance,the frequency amplitude response drop 137 dB from 430 Hz to 500 Hz.A test system is build up,and the result shows that the signal to noise ratio of this system is better than 110 dB,which meets the demand of seismic data acquisition system.