基于FPGA的车道偏移告警系统

Lane departure warning system based on FPGA

为了解决传统的机器视觉处理系统在安全驾驶辅助系统的应用中遇到的成本和性能挑战,设计了一种以FPGA为处理核心的车道偏移告警系统,研究了车道线提取和车道偏移告警算法,并对其进行RTL级实现,实现了快速并行处理。通过搭建SOPC系统,集成了抬头显示系统,减少了额外的处理器成本,能够给驾驶员提供更加安全的驾驶体验。该方案成本低于传统的DSP视觉处理平台,系统的图像处理速率最高可以达到1157帧/秒,满足实时性要求。

This paper designs a lane departure warning system which takes FPGA as process core,in order to solve cost and performance of the traditional machine vision processing system.Then it researches on the lane line extracting and lane departure warning algorithm and realizes the parallel algorithm through RTL level design,and sets up the SOPC system which integrates the head up display system.The design can reduce the extra processor,and supply more secure driving experience.The design can cost less than the traditional visual processing DSP platform,and system can meet the real-time whose image processing rate can reach 1157 frames per second.