摘要
采用自顶向下的设计方法,对高速同步串行接口电路进行了详细的研究。在寄存器配置单元中,通过多参数的设置实现高速同步串行接口的可配置,使用灵活,兼容性强。利用VHDL语言对SSC接口电路进行描述,并通过仿真和验证。采用TSMC 65nm工艺库,总线时钟为150MHz时,最大数据传输速率可达75Mbit/s,面积为11868um2,功耗为416.8uW,很好地满足了设计要求,可广泛应用于数字信号处理系统中。
A detailed study of high-speed synchronous serial interface circuit （SSC）, using top-down design, is presented. In the register configuration module, SSC can be configured through multi-parameter settings, with the use of flexible and strong com- patibility. The interface circuit is described with VHDL and is validated by simulation and verification, which based on TSMC＇s 65nm process, operating at 150MHz, the data transfer rate is up to 75Mbit/s with the area occupation of 11868 um2 and the power dissipation of 416.8uW. These parameters can meet the requirements of design well and the interface circuit is widely used in digital signal processing （DSP） systems.
出处
《计算机工程与设计》
CSCD
北大核心
2012年第4期1373-1377,共5页
Computer Engineering and Design
