基于FPGA高阶FIR滤波器的实现

Realization of high-order FIR filter based on FPGA

从FIR数字滤波器的基本结构模型出发,分析了FIR滤波器的设计思路及具体实现方法,详细介绍了FIR滤波器的分布式算法(DA)结构。通过分析计算,得到普通DA结构实现高阶滤波器会消耗大量的查找表资源,这样的资源消耗甚至令硬件资源不可接受。针对普通DA的不足,提出了改进型DA结构。并利用FPGA仿真软件分别对64阶FIR带通滤波器的两种改进型DA结构进行仿真,结果表明改进型DA结构所消耗的资源大幅度降低。从而验证了改进型DA结构在降低运算资源和提高性能等方面的优越性。

Proceeding from the basic structure of FIR digital filter model,the design ideas and the specific implementation of the FIR filter is analyzed,and the distributed algorithm（DA） structure of FIR digital filter is described.Based on nalysis and calculation,a conclusion that a large amount of look-up table（LUT） resources will be consumed when the the common DA structure realizes higher-order filter is achieved.Such a resource consumption even makes the hardware resource can＇t accept.For these deficiencies of the common DA,an improved DA structure is proposed.The two improved DA structures of 64-order FIR hand-pass filter were simulated with FPGA simulation software.The results show that the improved DA structure significantly reduces consumption of resources,and has obvious advantages in the aspects of reducing the computing resources and improving the performance.