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小尺寸应变Si/SiGe PMOSFET阈值电压及其电流电压特性的研究

Study of Threshold Voltage and I-V Characteristic for Small-Scaled Strained Si/SiGe PMOSFET
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摘要 针对Si/SiGe pMOSFET器件结构求解泊松方程,同时考虑器件尺寸减小所致的物理效应,如漏致势垒降低(DIBL)效应、短沟道效应(SCE)和速度过冲效应,获得了强反型时小尺寸P+多晶SiGe栅应变Si pMOSFET的阈值电压模型和I-V特性模型。运用Matlab对模型进行计算,获得阈值电压随多晶SiGe栅Ge组分、栅长、氧化层厚度、弛豫SiGe虚拟衬底Ge组分、掺杂浓度以及漏源偏压的变化规律,I-V特性计算结果表明MOS器件采用Si基应变技术将有更高的输出特性。用器件仿真软件ISETCAD对模型结构进行仿真,所得结果与Matlab计算结果一致,从而证明了该模型的正确性,为小尺寸应变Si MOS器件的分析设计提供了参考。 In this paper,based on solving Poisson equation to the structure of Si/SiGe pMOSFET with polycrystalline SiGe gate,its threshold voltage model and I-V electrical characteristic model are proposed.The secondary effects induced by scaling of the MOS device,such as drain-induced lowering barrier effect(DIBL),short-channel effect(SCE) and velocity overshoot effect,are also taken in account.By simulating the model with Matlab,the relationship between threshold voltage and relevant parameters,such as Ge content in P+ Poly SiGe gate,gate length,oxide thickness,Ge content in relax SiGe virtual substrates,doping concentration and drain bias,are obtained.The results of I-V characteristic shows that MOS device with strained Si as its channel has higher output characteristic.Finally,the evidence for the validity of our model is derived from the comparison of analytical results with the simulation data from the 2-D device simulator ISE.The proposed model can also be easily used for reasonable analysis and design of small-scaled Si/SiGe pMOSFET.
出处 《电子科技大学学报》 EI CAS CSCD 北大核心 2012年第2期311-316,共6页 Journal of University of Electronic Science and Technology of China
基金 国家部委资助项目(51308040203 6139801)
关键词 漏致势垒降低 金属氧化物半导体晶体管 硅锗合金 应变硅 阈值电压 DIBL MOS SiGe strained Si threshold voltage
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