UHF RFID标签基带处理器的ASIC设计

ASIC Design of Baseband Processor for UHF RFID Tag

提出了一款基于EPC Class1 Generation2协议的UHF RFID标签基带处理器。考虑到工作距离是无源标签的一个重要指标,要提高工作距离,就要降低标签功耗,采取了一系列低功耗措施,如2.56MHz和1.28MHz的双时钟策略、增加单元开关功能以及使用异步计数器等。设计采用TSMC 0.18μm工艺,工作电压为1.8V,功耗为6.4μW,版图尺寸为415μm×398μm。采用Xilinx的FPGA开发平台进行验证,测试结果满足C1G2协议要求。

An ASIC of baseband processor for UHF RFID tag was designed,which was compliant with EPC C1G2 protocol.In this design,a number of low power techniques were employed,including 2.56 MHz 1.28 MHz dual-clock strategy,unit switching function and asynchronous counter.Implemented in TSMC＇s 0.18 μm process,the baseband circuit had a power consumption of 6.4 μW at 1.8 V supply voltage,and its layout area was 415 μm × 398 μm.Functional test with FPGA of Xilinx indicated that the circuit met all the requirements of EPC C1G2 protocol.