LDPC译码器信道似然比信息存储模块优化设计

Optimized Design of LDPC Decoder for Channel Likelihood Ratio Information Memory Block

以CCSDS(太空数据系统咨询委员会)标准中1/2码率的LDPC码为例,分析了低密度奇偶校验码(LDPC)译码算法的特点,提出了在译码器的FPGA实现中采用乒乓操作的设计方法,优化译码器信道似然比信息存储模块结构,交替接收两帧数据,使译码器不间断地工作,提高了硬件资源利用率,使译码器的吞吐量增加一倍。

Based on LDPC（Low-Density Parity-Check） code with 1/2 code-rate in CCSDS（Consultative Committee for Space Data Systems） standard,characteristics of decoding algorithm for LDPC were analyzed.In FPGA implementation of the decoder,a ＂ping-pong operation＂ method was proposed to optimize the hardware structure of channel likelihood ratio information memory block,and receive two frame data alternately,which kept the decoder working uninterruptedly.The optimized design improved utilization ratio of hardware resource,and doubled throughput of the decoder.