漂移区覆盖高k薄膜的高压LDMOS器件优化设计

Optimization Design of LDMOS Device with Drift Region Covered by High-k Thin Film

为了获得高耐压、低导通电阻的横向双扩散MOSFET(LDMOS)器件,综合利用高介电常数(高k)薄膜技术和场板技术,设计出一种漂移区表面采用"高k薄膜+氧化层+场板"结构的功率器件,有效降低了PN结弯角高电场和场板边缘峰值电场。使用器件仿真工具MEDICI进行验证,并分析高k薄膜厚度、氧化层厚度、高k薄膜相对介电常数以及栅场板长度对器件性能的影响,最终实现了耐压达到820V、比导通电阻降至13.24Ω.mm2且性能稳定的LDMOS器件。

A high-voltage LDMOS device with drift region covered by high-k film ＋ oxide layer ＋ field plate structure was presented.To achieve high breakdown voltage and low on-resistance,high-k film and field plate were used to reduce peak field on the surface of reverse-biased PN junction and the edge of field plate.Simulation was made with MEDICI to investigate effects of structural parameters,such as high-k thin film thickness,oxide layer thickness,high-k permittivity and gate plate length,on performance of the device.Finally,an 820 V LDMOS with on-resistance down to 13.24 Ω·mm2 was implemented.