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基于双通道的NoC路由器系统级设计

A Design of Two-Channel Router for Network on Chip Based on System Level
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摘要 为提高路由器的并行处理能力,减少传输延时,提出并设计了一种包含GT通道与BE通道的双通道路由器.GT通道采用虚通道切换技术传输GT包,BE通道采用虫孔交换技术传输BE包,两通道之间的信号、存储、控制、传输都相互独立.在SystemC平台下进行系统级设计,采用XY维序路由算法、轮询仲裁机制、交换阵列开关控制矩阵的方法,完成数据包的路由与转发,实现GT包和BE包的并行传输. To improve the parallel processing ability of router and reduce the transmitting delay,this paper proposes and designs a two-channel router on system level.This router has two channels,one is GT channel for GT data packets,which adopts virtual channel switch technology,the other is BE channel for BE data packets,which adopts wormholes exchange technology.These two channels are independent on signal,storage,control and transmission.It is constructed on the SystemC platform,and adopts the XY-dimensional routing algorithm,the polling arbitration and the switch control fabric to realize the GT data packets and BE data packets transmitting parallel.
作者 段丽芬 吴宁
机构地区 南京航空航天大学电子信息工程学院
出处 《南京师范大学学报（工程技术版）》 CAS 2012年第1期52-56,共5页 Journal of Nanjing Normal University(Engineering and Technology Edition)
基金 国家自然科学基金(61076019)
关键词 片上网络 双通道路由器 SYSTEMC network on chip two-channel router SystemC
分类号 TP302.1 [自动化与计算机技术—计算机系统结构]
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参考文献6

  • 1Chai Song,Wu Chang,Li Yubai,et al.A NoC simulation and verification platform based on systemC[C]//2008Internaltion-al Conference on Computer Science and Software Engineering.Wuhan,2008:423-426.
  • 2Patooghy A,Miremadi S G.XYX:a power and performance efficient fault-tolerant routing algorithm for network on chip[C]//Proceedings of the200917th International Conference on Parallel,Distributed and Network-based Processing.Germany:Wei-mar,2009:245-251.
  • 3Robert Mullins,Andrew West,Simon Moore.The design and implementation of a low-latency on-chip network[C]//Asia and South Pacific Design Automation Conference(ASP-DAC).UK:Cambridge University,2006.
  • 4万玉鹏,吴宁.NoC路由单元的系统级设计[J].苏州科技学院学报（工程技术版）,2009,22(2):61-64. 被引量：3
  • 5岳培培,陈杰,刘建,SHERAZ ANJUM.应用于片上网络的双通道路由器[J].电子科技大学学报,2009,38(2):309-312. 被引量：3
  • 6Srinivasan Murali,Luca Benini.Analysis of error recovery schemes for networks on chips[J].Design and Test of Computers,2005,22(5):434-442.

二级参考文献18

  • 1高明伦,杜高明.NoC:下一代集成电路主流设计技术[J].微电子学,2006,36(4):461-466. 被引量：31
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  • 8Cesax Albenes Zeferino, Marcio Eduardo Kxeutz. RASOC: A Router Soft-Core for Networks-on- Chip [C]//In Proc.Of DATE. Paris, IEEE, 2004:198-203.
  • 9Mullins R, West A, Moore S. The design and implementation of a low-latency on-chip network[C]//Asia and South Pacific Design Automation Conference (ASP-DAC), Piscataway, N J, USA:IEEE, 2006.
  • 10Mullins R, West A, Moore S. Low-latency virtual-channel routers for on-chip Networks[C]//Proceedings of the 31st Annual International Sym posium on Computer Architecture, Los Almitos, CA, USA:IEEE, 2004:188-197.

共引文献4

南京师范大学学报（工程技术版）
2012年 第1期

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