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基于FPGA的机载图形加速子系统设计与实现 被引量:1

Design and Implementation of Graphic Acceleration Display Subsystem Based on FPGA
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摘要 本文设计了一种用于飞机座舱的图形显示加速子系统,该子系统支持字符和2D图形的生成显示,并具有反走样处理功能。为了避免直接读写外部DDR2存储器导致的DDR2操作瓶颈,提出增加缓存模块存储中间计算结果的方法,将计算逻辑和输出逻辑分开,对比较耗时的输出操作进行优化和集中处理以形成流水线操作,以达到实时显示的目的。实际应用结果表明,本文提出的方法提高了图形显示性能,满足当前飞机中对显示画面质量及实时性的要求。 A graphic acceleration engine in aircraft cockpit display system is proposed in this paper.The generation and anti-aliasing processing of characters and 2D graphics are supported in the display system.To avoid the memory bottleneck caused by the direct operations of graphics acceleration engine to DDR2,the output module is separated from the calculate module and a cache is introduced to store the calculated results.By optimizing and centralizing the time-consuming output operations,a pipeline operation is formed to perform real-time display.The results of practical applications show that the proposed method improves the graphic performance,and meets the aircraft display quality and real-time requirements.
出处 《航空电子技术》 2011年第4期16-20,共5页 Avionics Technology
关键词 图形显示 加速 缓存 FPGA graphic display accelerate cache FPGA
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