摘要
采用CSMC 0.35μm工艺,通过在电源和带隙基准源电路间插入电流源缓冲级的方法,设计提高带隙基准源电源噪声抑制能力的带隙基准源.在最低工作电压不变的情况下,所设计的带隙基准电源大幅度提高了电路的电源抑制比,且功耗低.仿真结果表明:电源抑制比值为110dB/40dB,Iq=12μA,Vmin=2.4V,可作为模拟IP(知识产权)且易集成于单片系统中.
A band-gap voltage reference with a high power supply rejection ratio（PSSR） is designed by using CSMC 0.35 μm processing through the method of inserting current source buffer stage between power and band-gap reference circuit.The proposed band-gap reference greatly improve the circuits PSRR and with a low power cost,without changing the lowest working voltage.The simulation results show that,the PSRR with 100 dB/40 dB,Iq=12 μA,Vmin=2.4 V,which can be used as analog intellectual property（IP） and easily integrated in the system on a chip（SOC）.
出处
《华侨大学学报（自然科学版）》
CAS
北大核心
2012年第3期265-268,共4页
Journal of Huaqiao University(Natural Science)
基金
华侨大学科研基金资助项目(10HZR05)
关键词
带隙基准源
电源噪声抑制比
低工作电压
低功耗
模拟IP
bandgap reference
power supply rejection ratio
low working voltage
low-power consumption
analog intellectual property
