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数字直放站中DLMS算法的FPGA实现

FPGA Implementation of DLMS Algorithm for Digital Repeater
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摘要 在采用LMS算法实现回波抵消功能的同频数字直放站中,针对节省资源来降低成本的问题,结合Pipeline和Systolic技术,提出了复数DLMS算法的2倍复用结构。由测试结果可知,所提的结构在节省了一半乘法器资源的基础上实现了回波抵消功能。 To save resources and reduce cost for single frequency repeater,which uses LMS algorithm to cancel echo,two-replicated architecture of complex DLMS algorithm is presented,which combines pipeline and systolic technology. According to simulation results,the proposed architecture achieves echo cancellation under the condition of saving a half of multiplier resources.
出处 《电视技术》 北大核心 2012年第9期37-40,58,共5页 Video Engineering
基金 粤港关键领域重点突破项目(200920523300005)
关键词 数字直放站 回波抵消 DLMS算法 FPGA digital repeater echo cancellation DLMS algorithm FPGA
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参考文献8

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二级参考文献7

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