一种高速增益单元存储器的内建自测试方案

A BIST Scheme for High-speed Gain Cell eDRAM

介绍了一种用于测试高速增益单元嵌入式动态随机存储器的内建自测试方案。该方案包括了指令集设计和体系结构设计。四级指令流水线的引入使全速测试成为可能。该设计方案可以通过执行不同的测试指令,对待测存储器执行多种类型的测试,从而达到较高的故障覆盖率。该内建自测试模块被集成在了一个存储容量为8kb的增益单元嵌入式动态随机存储器芯片中,并在中芯国际0.13μm标准逻辑工艺下进行了流片验证。芯片测试结果表明,该内建自测试方案可以在多种测试模式下对待测存储器执行全速测试,提高了测试速度,降低了对自动测试设备的性能要求,提高了测试的效率。

A built-in self-test（BIST） scheme is presented for at-speed test of a novel gain cell-based embedded DRAM which can operate at the high frequency of 200 MHz.This BIST implementation consists of instruction set architecture（ISA） and hardware.A 4-stage instruction pipeline for instruction execution makes at-speed test possible.It can perform various kinds of tests by executing different instruction combinations so that high fault coverage can be guaranteed.An 8 kb gain cell memory with the BIST is fabricated in 0.13 μm CMOS technology.Silicon measurement on ATE（Automatic test equipment） shows that the BIST can perform at-speed test in various test modes.Introduction of the BIST module can improve test speed,reduce performance request for ATE and improve test efficiency.