FSA乘法器的设计与实现

The Design and Implementation of FSA Multiplier

鉴于有限状态机对于具有逻辑顺序和时序规律的事件能有清晰的描述,对传统乘法器设计进行改进。提出一种快速、低功耗的FSA乘法器设计。该设计使用VHDL语言进行实现,并在QuartusⅡ上通过了仿真。仿真结果表明基于状态机的与基于逻辑电路的设计相比,在运算过程中产生的功耗以及运算速度上有较大的改善。

Based on the traditional multiplier, a kind of high-speed and low-power FSA multiplier was proposed. The finite state automaton was introduced to design the multiplier, because it can clearly describe the events with a logic and timing sequence. The programming language-VHDL was used to achieve this design which was simulated in Quartus I ~ The simulation result shows that the design based on the finite state automaton has a better performance in power and speed compared to the design based on the logic circuit.