BLAKE算法的硬件实现研究

Implementation of BLAKE Hash Function on FPGA

随着对MD5和SHA1攻击方法的提出,美国国家标准技术研究所(NIST)组织启动了SHA-3的征集计划,目前已进入第3轮.BLAKE算法进入了最后一轮竞赛,文中首先综述了BLAKE算法从提交到目前为止在硬件评估方面的状况.在此基础上优化了BLAKE压缩函数在FPGA上实现的关键路径,并在FPGA平台上实现了BLAKE算法.和现有的BLAKE算法在FPGA上实现的吞吐率相比,文中实现结构的吞吐率又有提升.

Along with the development of network technologies,cryptographic hash functions are used to protect information integrity and authenticity in a wide range of applications.Due to the discovery of weaknesses in the widely deployed hash algorithms MD5 and SHA1,the U.S.National Institute of Standards and Technology started a public competition to develop the future standard SHA-3.In this paper,we first survey the hardware implementations of BLAKE which is one of the finalists of SHA-3 competition,and then optimize the critical path of the BLAKE algorithm.The new architecture achieved a better throughput.