LDPC硬件实现中的数据量化位数选择及其性能仿真

低密度奇偶校验(LDPC)码是基于稀疏校验矩阵的线性分组码,由于其优越的性能以及译码硬件实现的低复杂度,一直受到广泛关注。基于FPGA的译码硬件实现LDPC译码器的主要任务之一就是数据量化问题的解决。数据运算单元是整个译码器的核心,数据能否合理量化这一问题与该译码算法的可靠性、硬件电路的可实现性和译码性能密切相关。本文首先进行了译码算法的资源消耗分析,在综合考虑资源消耗和运算精度的基础上提出合理的量化数据选择,同时就量化数据位对译码器性能的影响进行了仿真。

Low-density parity-check code （LDPC） is one kind of linear grouping code based on sparse check matrices, for it＇s perfect performance and low complexity in decoding hardware realize, LDPC received extensive attention. The prime mission in decoding hardware realize based on FPGA is to solve data-measuring problem. Data operation is the most basic part of the whole decoding algorithm, proper measured or not of data relate to reliability of the whole decoding algorithm and maneuvera- bility and veracity of hardware circuit. The paper analysis the resource consumption properly and put forward reasonable measured-data selection according to overall considers resource consumption and operation precision.