期刊文献+

Scratch-concerned yield modeling for IC manufacturing involved with a chemical mechanical polishing process 被引量:1

Scratch-concerned yield modeling for IC manufacturing involved with a chemical mechanical polishing process
原文传递
导出
摘要 In existing integrated circuit (IC) fabrication methods,the yield is typically limited by defects generated in the manufacturing process.In fact,the yield often shows a good correlation with the type and density of the defect.As a result,an accurate defect limited yield model is essential for accurate correlation analysis and yield prediction.Since real defects exhibit a great variety of shapes,to ensure the accuracy of yield prediction,it is necessary to select the most appropriate defect model and to extract the critical area based on the defect model.Considering the realistic outline of scratches introduced by the chemical mechanical polishing (CMP) process,we propose a novel scratch-concerned yield model.A linear model is introduced to model scratches.Based on the linear model,the related critical area extraction algorithm and defect density distribution are discussed.Owing to higher correspondence with the realistic outline of scratches,the linear defect model enables a more accurate yield prediction caused by scratches and results in a more accurate total product yield prediction as compared to the traditional circular model. In existing integrated circuit (IC) fabrication methods, the yield is typically limited by defects generated in the manufacturing process. In fact, the yield often shows a good correlation with the type and density of the defect. As a result, an accurate defect limited yield model is essential for accurate correlation analysis and yield prediction. Since real defects exhibit a great variety of shapes, to ensure the accuracy of yield prediction, it is necessary to select the most appropriate defect model and to extract the critical area based on the defect model. Considering the realistic outline of scratches introduced by the chemical mechanical polishing (CMP) process, we propose a novel scratch-concerned yield model. A linear model is introduced to model scratches. Based on the linear model, the related critical area extraction algorithm and defect density distribution are discussed. Owing to higher correspondence with the realistic outline of scratches, the linear defect model enables a more accurate yield prediction caused by scratches and results in a more accurate total product yield prediction as compared to the traditional circular model.
出处 《Journal of Zhejiang University-Science C(Computers and Electronics)》 SCIE EI 2012年第5期376-384,共9页 浙江大学学报C辑(计算机与电子(英文版)
关键词 Chemical mechanical polishing (CMP) SCRATCH DEFECT Yield model Critical area Chemical mechanical polishing (CMP), Scratch, Defect, Yield model, Critical area
  • 相关文献

参考文献23

  • 1Allan, G.A., Walton, A.J., 1997. Efficient Critical Area Esti- mation for Arbitrary Defect Shapes. Proc. IEEE Int. Symp. on Defect and Fault Tolerance in VLSI Systems, p.20-28.
  • 2Allan, G.A., Walton, A.J., 1998. Critical area extraction for soft fault estimation. IEEE Trans. Semicond. Manuf, 11(1): 146-154. [doi:10.1109/66.661294].
  • 3Aytes, S.D., Armstrong, J.S., Mortensen, K.A., Mortensen, K.A., Russell, C.W., Ross, K.A., Giraud, J.E., Hooper, D.H., Alexander, H.M., Nelson, M.M., et al., 2003. Ex- perimental Investigation of the Mechanism for CMP Micro-scratch Formation. Proc. 15th Biennial Microe- lectronics Symp., p. 107-109.
  • 4Hess, C., Stroele, A.P., 1994. Modeling of real defect outlines and parameter extraction using a checkerboard test structure to localize defects. IEEE Trans. Semicond. Manuf., 7(3):284-292. [doi:l 0.1109/66.311331].
  • 5Hess, C., Weiland, L.H., 1996. Issues on the Size and Outline of Killer Defects and Their Influence on Yield Modeling. IEEE/SEML Advanced Semiconductor Manufacturing Conf., p.423-428.
  • 6Huang, J., Chen, H.C., Wu, J.Y., Lur, W., 1999. Investigation of CMP Micro-Scratch in the Fabrication of Sub-quarter Micron VLSI Circuit. Proc. Chemical Mechanical Pol- ishing-Multilevel of Interconnection Conf., p.77-79.
  • 7Jung, S.M., Uom, J.S., Cho, W.S., Bae, Y.J., Chung, Y.K., Yu, K.S., Kim, K.Y., Kim, K.T., 2001. A Study of Formation and Failure Mechanism of CMP Scratch Induced Defects on ILD in a W-damascene Interconnect SRAM Cell. IEEE 39th Annual Int. Reliability Physics Symp., p.42-47.
  • 8Khare, J.B., Maly, W., Thomas, M.E., 1994. Extraction of defect size distributions in an IC layer using test structure data. IEEE Trans. Semicond. Manuf, 7(3):354-368. [doi:10.1109/66.311339].
  • 9Lauther, U., 1981. An O(NlogN) Algorithm for Boolean Mask Operations. Proc. 18th Design Automation Conf., p.555- 560. [doi:10.1109/DAC.1981.1585410].
  • 10Luo, J.F., Domfeld, D.A., 2004. Integrated Modeling of Chemical Mechanical Planarization for Sub-micron In- tegrated Circuit Fabrication. Springer, NY, USA.

同被引文献1

引证文献1

二级引证文献2

相关作者

内容加载中请稍等...

相关机构

内容加载中请稍等...

相关主题

内容加载中请稍等...

浏览历史

内容加载中请稍等...
;
使用帮助 返回顶部