Design of dual-edge triggered flip-flops based on quantum-dot cellular automata

Quantum-dot cellular automata (QCA) technology has been widely considered as an alternative to complementary metal-oxide-semiconductor (CMOS) due to QCA's inherent merits.Many interesting QCA-based logic circuits with smaller feature size,higher operating frequency,and lower power consumption than CMOS have been presented.However,QCA is limited in its sequential circuit design with high performance flip-flops.Based on a brief introduction of QCA and dual-edge triggered (DET) flip-flop,we propose two original QCA-based D and JK DET flip-flops,offering the same data throughput of corresponding single-edge triggered (SET) flip-flops at half the clock pulse frequency.The logic functionality of the two proposed flip-flops is verified with the QCADesigner tool.All the proposed QCA-based DET flip-flops show higher performance than their SET counterparts in terms of data throughput.Furthermore,compared with a previous DET D flip-flop,the number of cells,covered area,and time delay of the proposed DET D flip-flop are reduced by 20.5%,23.5%,and 25%,respectively.By using a lower clock pulse frequency,the proposed DET flip-flops are promising for constructing QCA sequential circuits and systems with high performance.

Quantum-dot cellular automata （QCA） technology has been widely considered as an alternative to complementary metal-oxide-semiconductor （CMOS） due to QCA＇s inherent merits. Many interesting QCA-based logic circuits with smaller feature size, higher operating frequency, and lower power consumption than CMOS have been presented. However, QCA is limited in its sequential circuit design with high performance flip-flops. Based on a brief introduction of QCA and dual-edge triggered （DET） flip-flop, we propose two original QCA-based D and JK DET flip-flops, offering the same data throughput of corresponding single-edge triggered （SET） flip-flops at half the clock pulse frequency. The logic functionality of the two proposed flip-flops is verified with the QCADesigner tool. All the proposed QCA-based DET flip-flops show higher performance than their SET counterparts in terms of data throughput. Furthermore, compared with a previous DET D flip-flop, the number of cells, covered area, and time delay of the proposed DET D flip-flop are reduced by 20.5%, 23.5%, and 25%, respectively. By using a lower clock pulse frequency, the proposed DET flip-flops are promising for constructing QCA sequential circuits and systems with high oerformance.