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基于谐波混频的微波低相噪锁相设计

Design of low phase noise microwave phase-locked source based on harmonic mixer
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摘要 该设计通过谐波混频的方式实现常规分频式锁相环所难以实现的低相噪指标。在理论分析的基础之上,提出微波低相噪锁相环设计方案,制定实际电路结构,通过对电路的调试达到在5.5GHz频点输出-111.30dBc/Hz@10kHz的相噪指标和-67.33dBc的杂散指标。验证了通过谐波混频的方式实现微波低相噪锁相的可行性。 The purpose of research is to obtain lowphase noise in the Phase locked loops by means of harmonic mixer,which is impossible with the method of traditional PLLS.On the basis of theory analysis,we introduces the design project design of low phase noise microwave phase-locked source and make the circuit structure to identify this theory.After adjusted,the circuit reach to a ideal result.phase noise is-111.30 dBc/Hz@10KHz and Spur compression is-67.30 dB at the 5.5 GHz frequency point.
作者 冯国兴
出处 《现代电子技术》 2012年第9期179-180,190,共3页 Modern Electronics Technique
关键词 低相噪 谐波混频 锁相源 杂散指标 lowphase noise harmonic mixing phase-locked source
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参考文献13

  • 1郭仿军.小数分频锁相环的杂散分析[J].重庆邮电学院学报(自然科学版),2002,14(2):84-87. 被引量:10
  • 2RHEE W, SONG B, ALI A. A 1.1 GHz CMOS fractional- N frequency synthesizer with a 3b third-order delta-sig- mamodulator [J]. IEEE Journal of Solid-State Circuits, 2000 (10) : 1453-1460.
  • 3MILLER B, CONLEY R J. A multiple modulator fractional divider [J]. IEEE Trans. on Instrumentation and Measure- ment, 1991, 40(6): 578-583.
  • 4GALTON I. Delta-sigma data conversion in wireless trans- ceivers [J]. IEEE Trans. on Microwave Theory and Tech- niques, 2002, 50(1): 302-315.
  • 5SHAHRUZ S M. Design of high-performance phase-locked loops and synthesizers [J]. Journal of Sound and Vibra- tion, 2002, 244(2): 367-377.
  • 6LINYi-jing SHENGShi-min.AnovelchargepumpinPLL.北京大学学报:自然科学版,2002,38(3):284-286.
  • 7WILLIAM C L, CHAK M C. Performance measures for phase-locked loops-a tutorial [J]. IEEE Transactions on Communications, 1982, 30(10) : 2224-2227.
  • 8EIJI Yoshida, MASATAKA Nakazawa. Measurement of the timing jitter and pulse energy fluctuation of a PLL regeneratively mode-locked fiber laser [J]. IEEE Photonics Technology Letters, 1999, 11(5): 548-550.
  • 9陈菊芳,岳丽娟,彭建华.超混沌五阶自治电路的设计及实验结果[J].东北师大学报(自然科学版),2000,32(3):26-29. 被引量:12
  • 10张厥盛,万心平.锁相技术[M].西安:电子科技大学出版社,1993:113-164.

二级参考文献18

  • 1蒋代林,鲁昆生.多信道无绳电话中的锁相频率合成器[J].通信技术与发展,1996(4):42-48. 被引量:1
  • 2万心平.通讯工程中的锁相环路[M].西安:西北电讯工程学院,1980..
  • 3Allstot D J, Liang G, Yang H C. Current-mode logic techniques for CMOS mixed-mode ASIC's. Proc IEEE Custom Illtegrated Circuits Conf, 1991. 25 (2) : 1 - 4.
  • 4Gardner F M. Chrage-pump phase-lock loops. IEEE Trans Comun, 1980;COM-28(11):1 849-1 858.
  • 5Kim Sungjoon, Lee Kyeongho, Yongsam Moon, et al.A 960-Mb/s/pin interface for Skew-Tolerant bus using low Jitter PLL. IEEE Journal of Solid-State Circuits,1997 ;32(5) :691- 700.
  • 6Ingino Joseph M. A 4GHz 40dB PSRR PLL for an SOC application. 2001 IEEE International Solid-State Circuits Conference, 2001 : 392- 393.
  • 7Razavi Behzad. Design of Analog CMOS Integrated Circuits, McGraw-Hill, 2001 : 532- 576.
  • 8Matsuda Higura. PLL performance simulation and design. National Semiconductor, 2001 : 77- 82.
  • 9邓忠礼,光同步数字系统测试,1998年
  • 10韦乐平,光同步数字传输网,1996年

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