2CHENG K-T, AGRAWAL V D. An Economical Scan Design for Sequential Logic Test Generation[C]//Proc of 19'h International Symposium on Fault-Tolerant Computing. Chicago, USA: IEEE, 1989: 28-35.
3AGRAWAL Vishwani D, KIME Charles R, SALUJA Kewal K. A Tutorial on Built-In Self-Test, Part 2: Applications[J]. IEEE Design & Test of Computers, 1993, 10(2): 69-77.
4IEEE Standard 1149.1-2001, Standard Test Access Port and Boundary-Scan Architecture[S].
5ORIAN Y. Test Requirements for Embedded Core-based ,stem and IEEE P15OO[C]//Proc IEEE Int Test Conf. Los ngeles, CA: IEEE, 1997: 191-199.
