可控脉冲信号发生器的设计

Design of Controllable Pulse Signal Generator

数字信号由于具有抗干扰能力强、无噪声积累,便于存储、处理和交换等一系列优点,已经成为现代控制领域的主要处理信号.要求改变脉冲信号的周期、占空比和输出脉冲个数可控的电路模块在很多控制领域都有应用.本文介绍了一种基于FPGA芯片的可控输出信号周期、占空比和信号个数的设计方法.应用时钟管理模块对输入时钟进行倍频来提高输出信号的周期范围和精度;调用IP核来完成相应的数学运算;应用两个可控减计数器来控制每一周期内高低电平的持续时间;应用数量控制计数器对输出的脉冲进行计数,控制输出量.该设计运行在ALTERA公司的clcyone芯片上,取得良好的效果,具有灵活高效的优点.

Digital signal has been the chief processing signal in the field of modern controlling because it has a series of advantages such as strong anti-interference,noise-free accumulation and easy to store,process and exchange.There are many applications in requirements to change the cycle of the pulse signal,duty cycle and the module of output pulse controlled.This paper discusses a method to finish these works based on the FPGA.We increase the cycle of the output signal range and accuracy by using clock management module;call IP core to complete the appropriate math problems;control the duration of each cycle of high and low by using two controllable down counter;counter the output and control the output.The design achieves a good result on the chip made of ALTERA company and it has the feature of flexibility.