基于深亚微米工艺的ESD保护器件优化设计

Design optimization of ESD protection device based on submicron CMOS process

集成电路工艺目前已经发展到超深亚微米水平,静电放电危害变得更加突出。针对这一问题,首先介绍了基于CMOS工艺的静电放电保护电路结构及性能,并在此基础上讨论ESD电路的设计、仿真方法。这里以常用保护器件栅极接地NMOS(GGNMOS)为例,分析了尺寸参数对ESD保护性能的影响;同时给出了一个符合ESD保护性能要求的优化设计方案。器件采用TCAD软件Sentaurus进行工艺仿真和物理特性模拟,对设计给予了验证,结果显示在0.18μm工艺下本设计达到ESD防护指标。

AS IC fabrication technology has come into deep-submicron and nanometer processing stage,ESD is becoming more prominent.ESD protection circuit and design methodology are analyzed based on CMOS process.As an example,the dimension parameter influence of commonly used protection device GGNMOS is discussed.Meanwhile,an optimized design scheme,which is conformed ESD protection performance requirements,is given.TCAD software sentaurus is used to simulate and verify the design,and the simulation results shows that the ESD protection standard is achieved in 0.18μm process technology.