一种超深亚微米SRAM存储单元的设计方法

A Design Method of the SRAM Core-cell in Very Deep Sub-micron Technology

首先分析了静态随机存储器(SRAM)6T存储单元结构的基本工作原理,为缩短仿真时间,构建了一种简化的SRAM电路,并通过仿真证实了此简化电路具有正确的读、写功能.鉴于本文仿真在TSMC180nm工艺下进行,且结合存储单元的W/L比例限制,最终选取了一组可行的晶体管尺寸.本文仿真均通过Hspice电路仿真软件进行仿真、验证.

The basic principles of a SRAM（Static random access memory） 6 Transistor（6T） core-cell were analyzed and summarized.In order to reduce the simulation time,the considered memories were simplified version including a reduced set of core-cells and peripheral circuits.With this simplified circuit,the simulation shows that the circuit has the correct read and write function.Due to the simulation carried out in TSMC 180nm process and the core-cells with W/L ratio limit,the size of the transistors was chosen.All the simulations were verified by Hspice.